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fsbb20ch60 motion spm? 3 series january 2014 ?2006 fairchild semiconductor corporation 1 www.fairchildsemi.com fsbb20ch60 rev. c6 fsbb20ch60 motion spm ? 3 series features ? ul certified no. e209204 (ul1557) ? 600 v - 20 a 3-phase igbt inverter with integral gate drivers and protection ? low-loss, short-circuit rated igbts ? very low thermal resistance using al 2 o 3 dbc sub- strate ? dedicated vs pins simplify pcb layout ? separate open-emitter pins from low-side igbts for three-phase current sensing ? single-grounded power supply ? isolation rating: 2500 v rms / min. applications ? motion control - home appliance / industrial motor related resources ? an-9035 - motion spm 3 series ver.2 user?s guide general description fsbb20ch60 is a motion spm ? 3 module providing a fully-featured, high-performanc e inverter output stage for ac induction, bldc, and pmsm motors. these mod- ules integrate optim ized gate drive of the built-in igbts to minimize emi and losses, while also providing multi- ple on-module protection features including under-volt- age lockouts, over-current shutdown, and fault reporting. the built-in, high-speed hvic requires only a single sup- ply voltage and translates t he incoming logic-level gate inputs to the high-voltage, high-current drive signals required to properly drive the module's internal igbts. separate negative igbt terminals are available for each phase to support the widest variety of control algorithms. package marking and ordering inform ation figure 1. package overview device device marking package packing type quantity fsbb20ch60 fsbb20ch60 spmca-027 rail 10
fsbb20ch60 motion spm? 3 series ?2006 fairchild semiconductor corporation 2 www.fairchildsemi.com fsbb20ch60 rev. c6 integrated power functions ? 600 v - 20 a igbt inverter for three-phase dc / ac power conversion (please refer to figure 3) integrated drive, protectio n and system control functions ? for inverter high-side igbts: gate drive circ uit, high-voltage isolated high-speed level shifting control circuit under-voltage lock-out protection (uvlo) note: available bootstrap circuit exam ple is given in figures 10 and 11. ? for inverter low-side igbts: gate driv e circuit, short-circuit protection (scp) control supply circuit under-v oltage lock-out protection (uvlo) ? fault signaling: corresponding to uvlo (low-side supply) and sc faults ? input interface: active-high interface, wor ks with 3.3 / 5 v logic, schmitt-trigger input pin configuration figure 2. top view (21) n u (22) n v (23) n w (27) p u (25) v (26) w case temperature (t c ) detecting point dbc substrate (21) n u (22) n v (23) n w (27) p (24) (25) v (26) w case temperature (t c ) detecting point (1) v cc(l) (2) com (3) in (ul) (4) in (vl) (5) in (wl) (6) v fo (15) v b(v) (16) v s(v) (17) in (wh) (18) v cc(wh) (19) v b(w) (20) v s(w) (7) c fod (8) c sc (9) in (uh) (10) v cc(uh) (11) v b(u) (12) v s(u) (13) in (vh) (14) v cc(vh) (1) v cc(l) (2) com (3) in (ul) (4) in (vl) (5) in (wl) (6) v fo (15) v b(v) (16) v s(v) (17) in (wh) (18) v cc(wh) (19) v b(w) (20) v s(w) (7) c fod (8) c sc (9) in (uh) (10) v cc(uh) (11) v b(u) (12) v s(u) (13) in (vh) (14) v cc(vh) 13.7 19.2 (21) n u (22) n v (23) n w (27) p u (25) v (26) w case temperature (t c ) detecting point dbc substrate (21) n u (22) n v (23) n w (27) p (24) (25) v (26) w case temperature (t c ) detecting point (1) v cc(l) (2) com (3) in (ul) (4) in (vl) (5) in (wl) (6) v fo (15) v b(v) (16) v s(v) (17) in (wh) (18) v cc(wh) (19) v b(w) (20) v s(w) (7) c fod (8) c sc (9) in (uh) (10) v cc(uh) (11) v b(u) (12) v s(u) (13) in (vh) (14) v cc(vh) (1) v cc(l) (2) com (3) in (ul) (4) in (vl) (5) in (wl) (6) v fo (15) v b(v) (16) v s(v) (17) in (wh) (18) v cc(wh) (19) v b(w) (20) v s(w) (7) c fod (8) c sc (9) in (uh) (10) v cc(uh) (11) v b(u) (12) v s(u) (13) in (vh) (14) v cc(vh) (1) v cc(l) (2) com (3) in (ul) (4) in (vl) (5) in (wl) (6) v fo (15) v b(v) (16) v s(v) (17) in (wh) (18) v cc(wh) (19) v b(w) (20) v s(w) (7) c fod (8) c sc (9) in (uh) (10) v cc(uh) (11) v b(u) (12) v s(u) (13) in (vh) (14) v cc(vh) (1) v cc(l) (2) com (3) in (ul) (4) in (vl) (5) in (wl) (6) v fo (15) v b(v) (16) v s(v) (17) in (wh) (18) v cc(wh) (19) v b(w) (20) v s(w) (7) c fod (8) c sc (9) in (uh) (10) v cc(uh) (11) v b(u) (12) v s(u) (13) in (vh) (14) v cc(vh) 13.7 19.2 13.7 19.2
fsbb20ch60 motion spm? 3 series ?2006 fairchild semiconductor corporation 3 www.fairchildsemi.com fsbb20ch60 rev. c6 pin descriptions pin number pin name pin description 1v cc(l) low-side common bias voltage for ic and igbts driving 2 com common supply ground 3in (ul) signal input for low-side u-phase 4in (vl) signal input for low-side v-phase 5in (wl) signal input for low-side w-phase 6v fo fault output 7c fod capacitor for fault output duration selection 8c sc capacitor (low-pass filter) for shor t-circuit current detection input 9in (uh) signal input for high-side u-phase 10 v cc(uh) high-side bias voltage for u-phase ic 11 v b(u) high-side bias voltage for u-phase igbt driving 12 v s(u) high-side bias voltage ground for u-phase igbt driving 13 in (vh) signal input for high-side v-phase 14 v cc(vh) high-side bias voltage for v-phase ic 15 v b(v) high-side bias voltage for v-phase igbt driving 16 v s(v) high-side bias voltage ground fo r v-phase igbt driving 17 in (wh) signal input for high-side w phase 18 v cc(wh) high-side bias voltage for w-phase ic 19 v b(w) high-side bias voltage for w-phase igbt driving 20 v s(w) high-side bias voltage ground for w-phase igbt driving 21 n u negative dc-link input for u-phase 22 n v negative dc-link input for v-phase 23 n w negative dc-link input for w-phase 24 u output for u-phase 25 v output for v-phase 26 w output for w-phase 27 p positive dc-link input
fsbb20ch60 motion spm? 3 series ?2006 fairchild semiconductor corporation 4 www.fairchildsemi.com fsbb20ch60 rev. c6 internal equivalent circ uit and input/output pins figure 3. internal block diagram 1st notes: 1. inverter low-side is composed of three igbts, freewheeling diodes for each igbt, and one control ic. it has gate drive and p rotection functions. 2. inverter power side is composed of four inverter dc-link input terminals and three inverter output terminals. 3. inverter high-side is composed of three igbts, freewheeling diodes, and three drive ics for each igbt. com vcc in(ul) in(vl) in(w l) vfo c(fod) c(sc) out(ul) out(vl) out(wl) n u (21) n v (22) n w (23) u (24) v (25) w (26) p (27) (20) v s(w) (19) v b(w) (16) v s(v) (15) v b(v) (8) c sc (7) c fod (6) v fo (5) in (w l) (4) in (vl) (3) in (ul) (2) com (1) v cc(l) vcc vb out com vs in vb vs out in com vcc vcc vb out com vs in (18) v cc(wh) (17) in (w h) (14) v cc(vh) (13) in (vh) (12) v s(u) (11) v b(u) (10) v cc(uh) (9) in (uh) v sl
fsbb20ch60 motion spm? 3 series ?2006 fairchild semiconductor corporation 5 www.fairchildsemi.com fsbb20ch60 rev. c6 absolute maximum ratings (t j = 25c, unless otherwise specified.) inverter part 2nd notes: 1. the maximum junction temperature rating of the power chips integrated within the motion spm ? 3 product is 150 ? c (at t c ? 100 ? c). however, to insure safe operation of the motion spm 3 product, the average junction temperature should be limited to t j(ave) ? 125 ? c (at t c ? 100 ? c) control part total system thermal resistance 2nd notes: 2. for the measurement point of case temperature(t c ), please refer to figure 2. symbol parameter conditions rating unit v pn supply voltage applied between p- n u , n v , n w 450 v v pn(surge) supply voltage (surge) applied between p- n u , n v , n w 500 v v ces collector - emitter voltage 600 v i c each igbt collector current t c = 25c 20 a i cp each igbt collector current (peak) t c = 25c, under 1ms pulse width 40 a p c collector dissipation t c = 25c per chip 61 w t j operating junction temperature (2nd note 1) -20 ~ 125 c symbol parameter conditions rating unit v cc control supply voltage applied between v cc(uh) , v cc(vh) , v cc(wh) , v cc(l) - com 20 v v bs high-side control bias voltage applied between v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) 20 v v in input signal voltage applied between in (uh) , in (vh) , in (wh) , in (ul) , in (vl) , in (wl) - com -0.3 ~ 17 v v fo fault output supply voltage applied between v fo - com -0.3 ~ v cc +0.3 v i fo fault output current sink current at v fo pin 5 ma v sc current-sensing input voltage applied between c sc - com -0.3 ~ v cc +0.3 v symbol parameter conditions rating unit v pn(prot) self-protection supply voltage limit (short-circuit protection capability) v cc = v bs = 13.5 ~ 16.5 v t j = 125c, non-repetitive, < 2 ? s 400 v t c module case operation temperature -20 ? c ?? t j ? 125 ? c, see figure 2 -20 ~ 100 c t stg storage temperature -40 ~ 125 c v iso isolation voltage 60 hz, sinus oidal, ac 1 minute, connect pins to heat sink plate 2500 v rms symbol parameter condition min. typ. max. unit r th(j-c)q junction to case thermal resistance inverter igbt part (per 1 / 6 module) - - 1.63 c/w r th(j-c)f inverter fwd part (per 1 / 6 module) - - 2.55 c/w
fsbb20ch60 motion spm? 3 series ?2006 fairchild semiconductor corporation 6 www.fairchildsemi.com fsbb20ch60 rev. c6 electrical characteristics (t j = 25c, unless otherwise specified.) inverter part 2nd notes: 3. t on and t off include the propagation delay of the internal drive ic. t c(on) and t c(off) are the switching time of igbt itself under th e given gate driving condition internally. for the detailed information, please see figure 4. figure 4. switching time definition symbol parameter conditions min. typ. max. unit v ce(sat) collector - emitter saturation voltage v cc = v bs = 15 v v in = 5 v i c = 20 a, t j = 25c - - 2.3 v v f fwdi forward voltage v in = 0 v i c = 20 a, t j = 25c - - 2.1 v hs t on switching times v pn = 300 v, v cc = v bs = 15 v i c = 20 a v in = 0 v ? 5 v, inductive load (2nd note 3) -0.48- ? s t c(on) -0.30- ? s t off -0.93- ? s t c(off) -0.52- ? s t rr -0.10- ? s ls t on v pn = 300 v, v cc = v bs = 15 v i c = 20 a v in = 0 v ? 5 v, inductive load (2nd note 3) -0.63- ? s t c(on) -0.30- ? s t off -1.01- ? s t c(off) -0.51- ? s t rr -0.10- ? s i ces collector - emitter leakage current v ce = v ces - - 250 ? a v ce i c v in t on t c(on) v in(on) 10% i c 10% v ce 90% i c 100% i c t rr 100% i c 0 v ce i c v in t off t c(off) v in(off) 10% v ce 10% i c (a) turn-on (b) turn-off
fsbb20ch60 motion spm? 3 series ?2006 fairchild semiconductor corporation 7 www.fairchildsemi.com fsbb20ch60 rev. c6 electrical characteristics (t j = 25c, unless otherwise specified.) control part 2nd notes: 4. short-circuit protection is functioning only at the low-sides. 5. the fault-out pulse width t fod depends on the capacitance value of c fod according to the following approximate equation: c fod = 18.3 x 10 -6 x t fod [f] recommended oper ating conditions symbol parameter conditions min. typ. max. unit i qccl quiescent v cc supply current v cc = 15 v in (ul, vl, wl) = 0 v v cc(l) - com - - 23 ma i qcch v cc = 15 v in (uh, vh, wh) = 0 v v cc(uh) , v cc(vh) , v cc(wh) - com - - 100 ? a i qbs quiescent v bs supply current v bs = 15 v in (uh, vh, wh) = 0 v v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) - - 500 ? a v foh fault output voltage v sc = 0 v, v fo circuit: 4.7 k ? to 5 v pull-up 4.5 - - v v fol v sc = 1 v, v fo circuit: 4.7 k ? to 5 v pull-up - - 0.8 v v sc(ref) short circuit current trip level v cc = 15 v (2nd note 4) 0.45 0.50 0.55 v uv ccd supply circuit under-voltage protection detection level 10.7 11.9 13.0 v uv ccr reset level 11.2 12.4 13.2 v uv bsd detection level 10.1 11.3 12.5 v uv bsr reset level 10.5 11.7 12.9 v t fod fault-out pulse width c fod = 33 nf (2nd note 5) 1.0 1.8 - ms v in(on) on threshold voltage applied between in (uh) , in (vh) , in (wh) , in (ul) , in (vl) , in (wl) - com 3.0 - - v v in(off) off threshold voltage - - 0.8 v symbol parameter conditions min. typ. max. unit v pn supply voltage applied between p - n u , n v , n w - 300 400 v v cc control supply voltage applied between v cc(uh) , v cc(vh) , v cc(wh) , v cc(l) - com 13.5 - 16.5 v v bs high-side bias voltage applied between v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) 13 - 18.5 v dv cc / dt, dv bs / dt control supply variation -1 - 1 v / ? s t dead blanking time for preventing arm-short for each input signal 2.5 - - ? s f pwm pwm input signal -20 ? c ?? t c ? 100c, -20 ? c ?? t j ?? 125c - - 20 khz v sen voltage for current sensing applied between n u , n v , n w - com (including surge voltage) -4 4 v
fsbb20ch60 motion spm? 3 series ?2006 fairchild semiconductor corporation 8 www.fairchildsemi.com fsbb20ch60 rev. c6 mechanical characteristics and ratings figure 5. flatness measurement position parameter conditions min. typ. max. unit mounting torque mounting screw: m3 recommended 0.62 n?m 0.51 0.62 0.72 n?m device flatness see figure 5 0 - +120 ? m weight - 15.00 - g ( + ) ( + ) ( + ) ( + )
fsbb20ch60 motion spm? 3 series ?2006 fairchild semiconductor corporation 9 www.fairchildsemi.com fsbb20ch60 rev. c6 time charts of protective function a1 : control supply voltage rises: after the voltage rises uv ccr , the circuits start to operat e when next input is applied. a2 : normal operation: igbt on and carrying current. a3 : under-voltage detection (uv ccd ). a4 : igbt off in spite of control input condition. a5 : fault output operation starts. a6 : under-voltage reset (uv ccr ). a7 : normal operation: igbt on and carrying current. figure 6. under-voltage protection (low-side) b1 : control supply voltage rises: after the voltage reaches uv bsr , the circuits start to operat e when next input is applied. b2 : normal operation: igbt on and carrying current. b3 : under-voltage detection (uv bsd ). b4 : igbt off in spite of control input c ondition, but there is no fault output signal. b5 : under-voltage reset (uv bsr ). b6 : normal operation: igbt on and carrying current. figure 7. under-voltage protection (high-side) input signal output current fault output signal control supply voltage reset uv ccr protection circuit state set reset uv ccd a1 a3 a2 a4 a6 a5 a7 input signal output current fault output signal control supply voltage reset uv bsr protection circuit state set reset uv bsd b1 b3 b2 b4 b6 b5 high-level (no fault output)
fsbb20ch60 motion spm? 3 series ?2006 fairchild semiconductor corporation 10 www.fairchildsemi.com fsbb20ch60 rev. c6 (with the external shunt resistance and cr connection) c1 : normal operation: igbt on and carrying current. c2 : short-circuit current detection (sc trigger). c3 : hard igbt gate interrupt. c4 : igbt turns off. c5 : fault output timer operation starts: the pulse width of the fault output signal is set by the external capacitor c fo . c6 : input ?low?: igbt off state. c7 : input ?high?: igbt on state, but during the ac tive period of fault output, the igbt doesn?t turn on. c8 : igbt off state. figure 8. short-circuit protec tion (low-side operation only) internal igbt gate - emitter voltage lower arms control input output current sensing voltage of shunt resistance fault output signal sc reference voltage cr circuit time constant delay sc protection circuit state set reset c6 c7 c3 c2 c1 c8 c4 c5
fsbb20ch60 motion spm? 3 series ?2006 fairchild semiconductor corporation 11 www.fairchildsemi.com fsbb20ch60 rev. c6 figure 9. recommended mcu i/o interface circuit 3rd notes: 1. rc coupling at each input (parts shown dotted) might change depending on the pwm control scheme in the application and the w iring impedance of the application?s printed circuit board. the motion spm ? 3 product input signal section integrates a 3.3 k ? ( typ.) pull-down resistor. therefore, when using an external filtering resistor, pay attention to the signal voltage drop at input terminal. 2. the logic input works with standard cmos or lsttl outputs. figure 10. recommended bootstrap operation circuit and parameters 3rd notes: 3. it would be recommended that the bootstrap diode, d bs , has soft and fast recovery characteristics. 4. the bootstrap resistor (r bs ) should be three times greater than r e(h) . the recommended value of r e(h) is 5.6 ? , but it can be increased up to 20 ?? (maximum) for a slower dv/ dt of high-side. 5. the ceramic capacitor placed between v cc - com should be over 1 ? f and mounted as close to the pins of the motion spm 3 product as possible. mcu spm com +5 v 1 nf 4.7 k ? ,, in (ul) in (vl) in (wl) ,, in (uh) in (vh) in (wh) v fo 100 ? 1 nf r pf = c pf = +15 v 22 f 0.1 f 1000 f1 f one-leg diagram of motion spm 3 product vcc in com vb ho vs vcc in com out inverter output p n these values depend on pwm control algorithm. d bs r bs r e(h) v sl
fsbb20ch60 motion spm? 3 series ?2006 fairchild semiconductor corporation 12 www.fairchildsemi.com fsbb20ch60 rev. c6 figure 11. typical application circuit 4th notes: 1. to avoid malfunction, the wiring of each input should be as short as possible (less than 2 - 3 cm). 2. by virtue of integrating an application-specific type of hvic inside the motion spm ? 3 product, direct coupling to mcu terminals without any optocoupler or transformer isola- tion is possible. 3. v fo output is open-collector type. this signal line should be pull ed up to the positive side of the 5 v power supply with approxi mately 4.7 k ? resistance (please refer to figure 9). 4. c sp15 of around seven times larger than bootstrap capacitor c bs is recommended. 5. v fo output pulse width should be determined by connecting an external capacitor (c fod ) between c fod (pin 7) and com (pin 2). (example : if c fod = 33 nf, then t fo = ???? ms (typ.)) please refer to the 2nd note 5 for calculation method. 6. input signal is active-high type. there is a 3.3 k ?? resistor inside the ic to pull down each input signal line to gnd. when employing rc coupling circuits, set up such rc cou- ple that input signal agree with turn-off / turn-on threshold voltage. 7. to prevent errors of the protection function, the wiring around r f and c sc should be as short as possible. 8. in the short-circuit protection circuit, please select the r f c sc time constant in the range 1.5 ~ 2 ? s. 9. each capacitor should be mounted as close to the pins of the motion spm 3 product as possible. 10. to prevent surge destruction, the wiring between the smoothing capacitor and the p & gnd pins should be as short as possib le. the use of a high-frequency non-inductive capacitor of around 0.1 ~ 0.22 ? f between the p & gnd pins is recommended. 11. relays are used in almost every systems of electrical equipme nt in home appliances. in these cases, there should be suffic ient distance between the mcu and the relays. 12. c spc15 should be over 1 ? f and mounted as close to the pins of the motion spm 3 product as possible. fault +15 v c bs c bsc r bs d bs c bs c bsc r bs d bs c bs c bsc r bs d bs c sp15 c spc15 c fod +5 v r pf c bpf r s m vdc c dcs gating uh gating vh gating wh gating wl gating vl gating ul c pf m c u r fu r fv r fw r su r sv r sw c fu c fv c fw w-phase current v-phase current u-phase current r f com vcc in(ul) in(vl) in(wl) vfo c(fod) c(sc) out(ul) out(vl) out(wl) n u (21) n v (22) n w (23) u (24) v (25) w (26) p (27) (20) v s(w) (19) v b(w) (16) v s(v) (15) v b(v) (8) c sc (7) c fod (6) v fo (5) in (wl) (4) in (vl) (3) in (ul) (2) com (1) v cc(l) vcc vb out com vs in vb vs out in com vcc vcc vb out com vs in (18) v cc(wh) (17) in (wh) (14) v cc(vh) (13) in (vh) (12) v s(u) (11) v b(u) (10) v cc(uh) (9) in (uh) input signal for short- circuit protection c sc r e(uh) v sl r e(vh) r e(wh)
fsbb20ch60 motion spm? 3 series ?2006 fairchild semiconductor corporation 13 www.fairchildsemi.com fsbb20ch60 rev. c6 detailed package outline drawings package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or data on the drawing and contact a fairchildsemicondu ctor representative to veri fy or obtain the most recent revision. package s pecifications do not expand the terms of fa irchild?s worldwide therm and conditions, specifically the the warranty therei n, which covers fairchild products. always visit fairchild semiconduct or?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/mo/mod27ba.pdf
fsbb20ch60 motion spm? 3 series ?2006 fairchild semiconductor corporation 14 www.fairchildsemi.com fsbb20ch60 rev. c6

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